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rev. 0.1 / apr. 2013 1 8gb ddr3 sdram 8gb ddr3 sdram (dual die package) lead-free&halogen-free (rohs compliant) h5tq8g43amr-xxc h5tq8g83amr-xxc h5tq8g63amr-xxc * sk hynix reserves the right to change pr oducts or specificat ions without notice.
rev. 0.1 / apr 2013 2 revision history revision no. history draft date remark 0.1 initial release apr. 2013
rev. 0.1 / apr 2013 3 description the h5tq8g43amr-xxc, h5tq8g83amr-xxc and h5tq8g63amr-xxc are a 8gb normal power double data rate iii (ddr3) synchronous dram, ideally suited for the main memory applications which requires large memory density and high bandwidt h and normal power operation at 1.5v. sk hynix 8gb ddr3 sdrams offer fully synchronous operat ions referenced to both rising and falling edges of the clock. while all addresses and control inputs are latched on the risi ng edges of the ck (falling edges of the ck), data, data strobes and write data masks in puts are sampled on both rising and falling edges of it. the data paths are internally pipelined and 8- bit prefetched to achieve very high bandwidth. device features and ordering information features ? vdd=vddq=1.5v +/- 0.075v ? fully differential clock inputs (ck, ck ) operation ? differential data strobe (dqs, dqs ) ? on chip dll align dq, dqs and dqs transition with ck ? transition ? dm masks write data-in at the both rising and falling ? edges of the data strobe ? all addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock ? programmable cas latency 5, 6, 7, 8, 9, 10, 11 and 13 supported ? programmable additive latency 0, cl-1, and cl-2 ? supported ? programmable cas write latency (cwl) = 5, 6, 7, 8, 9, 10 ? programmable burst length 4/8 with both nibble ? sequential and interleave mode ? bl switch on the fly ? 8banks ? average refresh cycle (tcase of 0 o c~ 95 o c) - 7.8 s at 0 o c ~ 85 o c - 3.9 s at 85 o c ~ 95 o c ? jedec standard 78ball fbga(x4/x8), 96ball fbga(x16 ? driver strength selected by emrs ? dynamic on die termination supported ? asynchronous reset pin supported ? zq calibration supported ? tdqs (termination data strobe) supported (x8 only) ? write levelization supported ? 8 bit pre-fetch ? this product in complian ce with the rohs directive.
rev. 0.1 / apr 2013 4 ordering information * xx means speed bin grade operating frequency part no. configuration package h5tq8g43amr-*xxc 2g x 4 78ball fbga h5tq8g83amr-*xxc 1g x 8 h5tq8g63amr-*xxc 512m x 16 96ball fbga grade frequency [mhz] remark cl5 cl6 cl7 cl8 cl9 cl10 cl11 cl12 cl13 -g7 667 800 1066 1066 -h9 667 800 1066 1066 1333 1333 -pb 667 800 1066 1066 1333 1333 1600 -rd 800 1066 1066 1333 1333 1600 1866
rev. 0.1 / apr 2013 5 package ballout/mec hanical dimension x4 package ball out (top view): 78ball fbga package note: nf (no function) - this is applied to balls only used in x4 configuration. 1 2 3 4 5 6 7 8 9 a vss vdd nc nf vss vdd a b vss vssq dq0 dm vssq vddq b c vddq dq2 dqs dq1 dq3 vssq c d vssq nf dqs vdd vss vssq d e vrefdq vddq nf nf nf vddq e f odt1 vss ras ck vss cke1 f g odt0 vdd cas ck vdd cke0 g h cs1 cs0 we a10/ap zq0 zq1 h j vss ba0 ba2 a15 vrefca vss j k vdd a3 a0 a12/ bc ba1 vdd k l vss a5 a2 a1 a4 vss l m vdd a7 a9 a11 a6 vdd m n vss reset a13 a14 a8 vss n 1 2 3 4 5 6 7 8 9 1 a b c d e f g h j k l m n populated ball ball not populated 2 789 (top view: see the balls through the package) 3
rev. 0.1 / apr 2013 6 x8 package ball out (top view): 78ball fbga package 1 2 3 4 5 6 7 8 9 a vss vdd nc nf/ tdqs vss vdd a b vss vssq dq0 dm/tdqs vssq vddq b c vddq dq2 dqs dq1 dq3 vssq c d vssq dq6 dqs vdd vss vssq d e vrefdq vddq dq4 dq7 dq5 vddq e f odt1 vss ras ck vss cke1 f g odt0 vdd cas ck vdd cke0 g h cs1 cs0 we a10/ap zq0 zq1 h j vss ba0 ba2 a15 vrefca vss j k vdd a3 a0 a12/ bc ba1 vdd k l vss a5 a2 a1 a4 vss l m vdd a7 a9 a11 a6 vdd m n vss reset a13 a14 a8 vss n 1 2 3 4 5 6 7 8 9 1 a b c d e f g h j k l m n populated ball ball not populated 2 789 (top view: see the balls through the package) 3
rev. 0.1 / apr 2013 7 x16 package ball out (top vi ew): 96ball fbga package 1 2 3 4 5 6 7 8 9 a vddq dqu5 dqu7 dqu4 vddq vss a b vssq vdd vss dqsu dqu6 vssq b c vddq dqu3 dqu1 dqsu dqu2 vddq c d vssq vddq dmu dqu0 vssq vdd d e vss vssq dql0 dml vssq vddq e f vddq dql2 dqsl dql1 dql3 vssq f g vssq dql6 dqsl vdd vss vssq g h vrefdq vddq dql4 dql7 dql5 vddq h j odt1 vss ras ck vss cke1 j k odt0 vdd cas ck vdd cke0 k l cs1 cs0 we a10/ap zq0 zq1 l m vss ba0 ba2 nc vrefca vss m n vdd a3 a0 a12/ bc ba1 vdd n p vss a5 a2 a1 a4 vss p r vdd a7 a9 a11 a6 vdd r t vss reset a13 a14 a8 vss t 1 2 3 4 5 6 7 8 9 1 a b c d e f g h j k l m n populated ball ball not populated 2 789 (top view: see the balls through the package) 3 p r t
rev. 0.1 / apr 2013 8 pin functional description symbol type function ck, ck input clock: ck and ck are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck . cke, (cke0), (cke1) input clock enable: cke high activates, and cke lo w deactivates, internal clock signals and device input buffers and output drivers. taking cke low provides precharge power-down and self-refresh operation (all banks idle), or active power-down (row active in any bank). cke is asynchronous for self-refresh exit. af ter vrefca and vrefdq have become stable during the power on and initia lization sequence, they must be maintained during all operations (including self-refresh). cke must be maintained high throughout read and write accesses. input buffers, excluding ck, ck , odt and cke, are disabled during power- down. input buffers, excluding cke, are disabled during self-refresh. cs , (cs 0), (cs 1), (cs 2), (cs 3) input chip select: all commands are masked when cs is registered high. cs provides for external rank selection on systems with multiple ranks. cs is considered part of the command code. odt, (odt0), (odt1) input on die termination: odt (registered high) enab les termination resistance internal to the ddr3 sdram. when enabled, odt is only applied to each dq, dqs, dqs and dm/tdqs, nu/tdqs (when tdqs is enabled via mode register a11=1 in mr1) signal for x4/x8 configurations. for x16 configuration, odt is applied to each dq, dqsu, dqsu , dqsl, dqsl , dmu, and dml signal. the odt pin will be ignored if mr1 is programmed to disable odt. ras . cas . we input command inputs: ras , cas and we (along with cs ) define the command being entered. dm, (dmu), (dml) input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high coincident with that inpu t data during a write access. dm is sampled on both edges of dqs. for x8 device, the function of dm or tdqs/tdqs is enabled by mode register a11 setting in mr1. ba0 - ba2 input bank address inputs: ba0 - ba2 define to which bank an active, read, write or precharge command is being applied. bank address also determines if the mode register or extended mode register is to be accessed during a mrs cycle. a0 - a15 input address inputs: provide the row address for active commands and the column address for read/write commands to select one location out of the memory array in the respective bank. (a10/ap and a12/bc have additional functions, see below). the address inputs also provide the op-code during mode register set commands. a10 / ap input auto-precharge: a10 is sampled during read/write commands to determine whether autoprecharge should be performed to the acce ssed bank after the read/write operation. (high: autoprecharge; low: no autoprec harge).a10 is sampled during a precharge command to determine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by bank addresses. a12 / bc input burst chop: a12 / bc is sampled during read and write commands to determine if burst chop (on-the-fly) will be performed. (high, no burst chop; low: burst choppe d). see command truth table for details.
rev. 0.1 / apr 2013 9 reset input active low asynchronous reset: reset is active when reset is low, and inactive when reset is high. reset must be high during normal operation. reset is a cmos rail-to-rail signal with dc high and low at 80% and 20% of v dd , i.e. 1.20v for dc high and 0.30v for dc low. dq input / output data input/ output: bi -directional data bus. dqu, dql, dqs, dqs , dqsu, dqsu , dqsl, dqsl input / output data strobe: output with read data, input wi th write data. edge-aligned with read data, centered in write data. the data strobe dqs, dqsl, and dqsu are paired with differential signals dqs , dqsl , and dqsu , respectively, to provide differential pair signaling to the system during reads and writes. ddr3 sdram su pports differential data strobe only and does not support single-ended. tdqs, tdqs output termination data strobe: tdqs/tdqs is applicable for x8 dr ams only. when enabled via mode register a11 = 1 in mr1, the dram wi ll enable the same termination resistance function on tdqs/tdqs that is applied to dqs/dqs . when disabled via mode register a11 = 0 in mr1, dm/tdqs will provide the data mask function and tdqs is not used. x4/x16 drams must disable the tdqs function via mode register a11 = 0 in mr1. nc no connect: no internal electr ical connection is present. nf no function v ddq supply dq power supply: 1.35 v +0.100/- 0.067 v v ssq supply dq ground v dd supply power supply: 1.35 v +0.100/- 0.067 v v ss supply ground v refdq supply reference voltage for dq v refca supply reference voltage for ca zq supply reference pin for zq calibration note: input only pins (ba0-ba2, a0-a15, ras , cas , we , cs , cke, odt, dm, and reset ) do not supply termination. symbol type function
rev. 0.1 / apr 2013 10 row and column address table 8gb note1: page size is the number of bytes of data delive red from the array to the internal sense amplifiers ? when an active command is registered. page size is per bank, calculated as follows: page size = 2 colbits * org ? 8 where colbits = the number of column address bits, org = the number of i/o (dq) bits configuration 2gb x 4 1gb x 8 512mb x 16 # of banks 8 8 8 bank address ba0 - ba2 ba0 - ba2 ba0 - ba2 auto precharge a10/ap a10/ap a10/ap bl switch on the fly a12/ bc a12/ bc a12/ bc row address a0 - a15 a0 - a15 a0 - a14 column address a0 - a9,a11 a0 - a9 a0 - a9 page size 1 1 kb 1 kb 2 kb
rev. 0.1 / apr 2013 11 x8 package pinout and addressing ? x16 package pinout and addressing ? odt cke zq cs dq 0-7 dm/tdqs,tdqs dqs,dqs ck,ck ,ca odt0 cke0 zq0 cs0 dq 0-7 ck,ck ,ras ,cas ,we ,an,ban dm/tdqs,tdqs dqs,dqs odt cke zq cs dq 0-7 dm/tdqs,tdqs dqs,dqs ck,ck ,ca odt1 cke1 zq1 cs1 4gb x 8 ddr3l 4gb x 8 ddr3l odt cke zq cs dq 0-15 dqsu,dqsu dqsl,dqsl ck,ck ,ca odt0 cke0 zq0 cs0 dq 0-15 ck,ck ,ras ,cas ,we ,an,ban dqsu,dqsu dqsl,dqsl odt cke zq cs dq 0-15 dqsu,dqsu dqsl,dqsl ck,ck ,ca odt1 cke1 zq1 cs1 4gb x 16 ddr3l 4gb x 16 ddr3l
rev. 0.1 / apr 2013 12 absolute maximum ratings absolute maximum dc ratings dram component operat ing temperature range absolute maximum dc ratings symbol parameter rating units notes vdd voltage on vdd pin relative to vss - 0.4 v ~ 1.80 v v 1,3 vddq voltage on vddq pin relative to vss - 0.4 v ~ 1.80 v v 1,3 v in , v out voltage on any pin relative to vss - 0.4 v ~ 1.80 v v 1 t stg storage temperature -55 to +100 o c1, 2 notes: 1. stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operat ion of the device at these or any other conditions above those indicated in the operational sections of this specif ication is not implied. exposure to absolute maximum rat - ing conditions for extended pe riods may affect reliability. 2. storage temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, please refer to jesd51-2 standard. 3. vdd and vddq must be within 300mv of each other at all times; and vref must not be greater than 0.6xvddq,when vdd and vddq are less than 500mv; vref may be equal to or less than 300mv. temperature range symbol parameter rating units notes t oper normal operating temperature range 0 to 85 o c 1,2 extended temperature range (optional) 85 to 95 o c1,3 notes: 1. operating temperature toper is the case surface temperat ure on the center / top side of the dram. for measure - ment conditions, please refer to the jedec document jesd51-2. 2. the normal temperature range specifies the temperatures where all dram specificatio ns will be supported. dur - ing operation, the dram case temperature must be maintained between 0 - 85 o c under all operating conditions. 3. some applications require operation of the dr am in the extended temperature range between 85 o c and 95 o c case temperature. full specifications are guaranteed in this range, but the following additional conditions apply: a. refresh commands must be doubled in frequency, therefore reducing the refresh interval trefi to 3.9 s. it is also possible to specify a component with 1x refresh (trefi to 7.8s) in the extended temperature range. please refer to the dimm spd for option availability b. if self-refresh operation is required in the extended temperature range, then it is mandatory to use the man - ual self-refresh mode with extended temperature range capability (mr2 a6 = 0b and mr2 a7 = 1b). ddr3 sdrams support extended temperature range and plea se refer to component da tasheet and/or the dimm spd for trefi requirements in the extended temperature range.
rev. 0.1 / apr 2013 13 ac & dc operating conditions recommended dc operating conditions recommended dc operating conditions symbol parameter rating units notes min. typ. max. vdd supply voltage 1.425 1.500 1.575 v 1,2 vddq supply voltage for output 1.425 1.500 1.575 v 1,2 notes: 1. under all conditions, vddq must be less than or equal to vdd. 2. vddq tracks with vdd. ac parameters are measured with vdd and vddq tied together.
rev. 0.1 / apr 2013 14 idd and iddq specification pa rameters and test conditions idd and iddq measurement conditions in this chapter, idd and iddq meas urement conditions such as test load and patterns are defined. figure 1. shows the setup and test load for idd and iddq measurements. ? idd currents (such as idd0, idd1, idd2n, idd2nt , idd2p0, idd2p1, idd2q, idd3n, idd3p, idd4r, idd4w, idd5b, idd6, idd6et and idd7) are measured as time-averaged currents with all vdd balls of the ddr3 sdram under test tied together. any iddq current is not included in idd currents. ? iddq currents (such as iddq2nt and iddq4r) are measured as time-averaged currents with all vddq balls of the ddr3 sdram under test tied toge ther. any idd current is not included in iddq cur - rents. ? attention: iddq values cannot be directly used to calculate io power of the ddr3 sdram. they can be used to support correlation of simulated io power to actual io po wer as outlined in figure 2. in dram module application, iddq cannot be measured separately si nce vdd and vddq are using one merged-power layer in module pcb. for idd and iddq measurements, the following definitions apply: ? ?0? and ?low? is defined as vin <= v ilac(max). ? ?1? and ?high? is defined as vin >= v ihac(max). ? ?mid_level? is defined as inputs are vref = vdd/2. ? timing used for idd and iddq measurement-loop patterns are provided in table 1. ? basic idd and iddq measurement co nditions are described in table 2. ? detailed idd and iddq measurement-loop patte rns are described in table 3 through table 10. ? idd measurements are done after properly initializi ng the ddr3 sdram. this includes but is not lim - ited to setting ? ron = rzq/7 (34 ohm in mr1); ? qoff = 0 b (output buffer enabled in mr1); ? rtt_nom = rzq/6 (40 ohm in mr1); ? rtt_wr = rzq/2 (120 ohm in mr2); ? tdqs feature disabled in mr1 ? attention: the idd and iddq measurement-loop patterns need to be executed at least one time before actual idd or iddq measurement is started. ? define d = { cs , ras , cas , we }:= {high, low, low, low} ? define d = { cs , ras , cas , we }:= {high, high, high, high}
rev. 0.1 / apr 2013 15 figure 1 - measurement setup and test load for idd and iddq (optional) measurements [note: dimm level output test load condition may be different from above] figure 2 - correlation from simulated channel io power to actual ch annel io power supported by iddq measurement v dd ddr3 sdram v ddq reset ck/ck dqs, dqs cs ras , cas , we a, ba odt zq v ss v ssq dq, dm, tdqs, tdqs cke r tt = 25 ohm v ddq /2 i dd i ddq (optional) application specific memory channel environment channel io power simulation iddq simulation iddq simulation channel io power number iddq test load correction
rev. 0.1 / apr 2013 16 table 1 -timings used for idd and iddq measurement-loop patterns table 2 -basic idd and iddq measurement conditions symbol ddr3-1066 ddr3-1333 ddr3-1600 ddr3-1866 unit 7-7-7 9-9-9 11-11-11 13-13-13 t ck 1.875 1.5 1.25 1.07 ns cl 7 9 11 13 nck n rcd 7 9 11 13 nck n rc 27 33 39 45 nck n ras 20 24 28 32 nck n rp 7 9 11 13 nck n faw 1kb page size 20 20 24 26 nck 2kb page size 27 30 32 33 nck n rrd 1kb page size 4 4 5 5 nck 2kb page size 6 5 6 6 nck n rfc -512mb 48 60 72 85 nck n rfc -1 gb 59 74 88 103 nck n rfc - 2 gb 86 107 128 150 nck n rfc - 4 gb 139 174 208 243 nck n rfc - 8 gb 187 234 280 328 nck symbol description i dd0 operating one bank active-precharge current ? cke: high; external clock: on; tck, nrc, nras, cl: see table 1; bl: 8 a) ; al: 0; cs : high between act and pre; command, address, bank address inputs: pa rtially toggling according to table 3; data io: mid-level; dm: stable at 0; bank activity: cycling with one bank active at a time: 0,0,1,1,2,2,... (see table 3); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 3. i dd1 operating one bank active-precharge current cke: high; external clock: on; tck, nrc, nras, nrcd, cl: see table 1; bl: 8 a) ; al: 0; cs : high between act, rd and pre; command, address; bank address inputs, data io: partially toggling according to table 4; dm: stable at 0; bank activity: cycling with on bank active at a time: 0,0,1,1,2,2,... (see table 4); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 4.
rev. 0.1 / apr 2013 17 i dd2n precharge standby current cke: high; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggl ing according to table 5; data io: mid_level; dm: stable at 0; bank activity: all banks closed; output bu ffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 5. i dd2nt precharge standby odt current cke: high; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggl ing according to table 6; data io: mid_level; dm: stable at 0; bank activity: all banks closed; output bu ffer and rtt: enabled in mode registers b) ; odt signal: tog- gling according to table 6; pattern details: see table 6. i dd2p0 precharge power-down current slow exit cke: low; external clock: on; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: mid_level; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: en abled in mode registers b) ; odt signal: stable at 0; precharge power down mode: slow exit c) i dd2p1 precharge power-down current fast exit cke: low; external clock: on; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: mid_level; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: en abled in mode registers b) ; odt signal: stable at 0; precharge power down mode: fast exit c) i dd2q precharge quiet standby current cke: high; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: mid_level; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0 i dd3n active standby current cke: high; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggl ing according to table 5; data io: mid_level; dm: stable at 0; bank activity: all banks open; output buff er and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 5. symbol description
rev. 0.1 / apr 2013 18 i dd3p active power-down current cke: low; external clock: on; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: mid_level; dm: stable at 0; bank activity: all banks open; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0 i dd4r operating burst read current cke: high; external clock: on; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : high between rd; command, address, bank address inputs: partially toggling accord ing to table 7; data io: seamless read data burst with different data between one bu rst and the next one according to table 7; dm: stable at 0; bank activity: all banks open, rd commands cycling through banks: 0,0,1,1,2, 2,...(see table 7); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 7. i dd4w operating burst write current cke: high; external clock: on; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : high between wr; command, address, bank address inputs: partially toggling accord ing to table 8; data io: seamless read data burst with different data between one bu rst and the next one according to table 8; dm: stable at 0; bank activity: all banks open, wr commands cycling throug h banks: 0,0,1,1,2,2,...(see table 8); output buf- fer and rtt: enabled in mode registers b) ; odt signal: stable at high; pattern details: see table 8. i dd5b burst refresh current cke: high; external clock: on; tc k, cl, nrfc: see table 1; bl: 8 a) ; al: 0; cs : high between ref; com- mand, address, bank address inputs: partially togglin g according to table 9; data io: mid_level; dm: stable at 0; bank activity: ref command every nref (see table 9); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 9. i dd6 self-refresh current: normal temperature range t case : 0 - 85 o c; auto self-refresh (asr): disabled d) ;self-refresh temperature range (srt): normal e) ; cke: low; external clock: off; ck and ck : low; cl: see table 1; bl: 8 a) ; al: 0; cs , command, address, bank address inputs, data io: mid_level; dm: stable at 0; bank activity: self-refresh operation; out- put buffer and rtt: enabled in mode registers b) ; odt signal: mid_level i dd6et self-refresh current: extended temperature range (optional) t case : 0 - 95 o c; auto self-refresh (asr): disabled d) ;self-refresh temperature range (srt): extend- ed e) ; cke: low; external clock: off; ck and ck : low; cl: see table 1; bl: 8 a) ; al: 0; cs , command, address, bank address inputs, data io: mid_level; dm: stable at 0; bank activity: extended tempera- ture self-refresh operation; output buff er and rtt: enabled in mode registers b) ; odt signal: mid_level symbol description
rev. 0.1 / apr 2013 19 a) burst length: bl8 fixed by mrs: set mr0 a[1,0]=00b b) output buffer enable: set mr1 a[12] = 0b; set mr1 a[ 5,1] = 01b; rtt_nom enable: set mr1 a[9,6,2] = 011b; rtt_wr enable: set mr2 a[10,9] = 10b c) precharge power down mode: set mr0 a12=0b for slow exit or mr0 a12 = 1b for fast exit d) auto self-refresh (asr): set mr2 a6 = 0b to disable e) self-refresh temperature range (srt): set mr2 a7 = 0b for normal or 1b for extended temperature range f) read burst type: nibble sequential, set mr0 a[3] = 0b i dd7 operating bank interleave read current cke: high; external clock: on; tck, nrc, nras, nrcd, nrrd, nfaw, cl: see table 1; bl: 8 a), f) ; al: cl- 1; cs : high between act and rda; command, address, bank address inputs: partially toggling accord- ing to table 10; data io: read data burst with di fferent data between one burst and the next one according to table 10; dm: stable at 0; bank acti vity: two times interleaved cycling through banks (0, 1,...7) with different addressing, wee table 10; ou tput buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 10. symbol description
rev. 0.1 / apr 2013 20 table 3 - idd0 measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are mid-level. b) dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 act0011000000 00 - 1,2 d, d1000000000 00 - 3,4 d , d 1111000000 00 - ... repeat pattern 1...4 until nras - 1, truncate if necessary nras pre0010000000 00 - ... repeat pattern 1...4 until n rc - 1, truncate if necessary 1*nrc+0 act 0 0 1 1 0 0 00 0 0 f 0 - 1*nrc+1, 2 d, d 1 0 0 0 0 0 00 0 0 f 0 - 1*nrc+3, 4 d , d 1111000000 f0 - ... repeat pattern 1...4 until 1*nrc + nras - 1, truncate if necessary 1*nrc+nras pre 0 0 1 0 0 0 00 0 0 f 0 - ... repeat pattern 1...4 until 2*nrc - 1, truncate if necessary 1 2*nrc repeat sub-loop 0, use ba[2:0] = 1 instead 2 4*nrc repeat sub-loop 0, use ba[2:0] = 2 instead 3 6*nrc repeat sub-loop 0, use ba[2:0] = 3 instead 4 8*nrc repeat sub-loop 0, use ba[2:0] = 4 instead 5 10*nrc repeat sub-loop 0, use ba[2:0] = 5 instead 6 12*nrc repeat sub-loop 0, use ba[2:0] = 6 instead 7 14*nrc repeat sub-loop 0, use ba[2:0] = 7 instead
rev. 0.1 / apr 2013 21 table 4 - idd1 measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are used according to rd commands, otherwise mid-level. b) burst sequence driven on each dq signal by read co mmand. outside burst operation, dq signals are mid_level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 act 0 0 1 1 0 0 00 0 0 0 0 - 1,2 d, d 1 0 0 0 0 0 00 0 0 0 0 - 3,4 d , d 1111 0 00000 0 0 - ... repeat pattern 1...4 until n rcd - 1, truncate if necessary nrcd rd 0 1 0 1 0 0 00 0 0 0 0 00000000 ... repeat pattern 1...4 until nr as - 1, truncate if necessary nras pre 0 0 1 0 0 0 00 0 0 0 0 - ... repeat pattern 1...4 until n rc - 1, truncate if necessary 1*nrc+0 act 0 0 1 1 0 0 00 0 0 f 0 - 1*nrc+1,2 d, d 1 0 0 0 0 0 00 0 0 f 0 - 1*nrc+3,4 d , d 1111 0 00000 f 0 - ... repeat pattern nrc + 1,...4 until n rc + nrce - 1, truncate if necessary 1*nrc+nrcd rd 0 1 0 1 0 0 00 0 0 f 0 00110011 ... repeat pattern nrc + 1,...4 until n rc + nras - 1, truncate if necessary 1*nrc+nras pre 0 0 1 0 0 0 00 0 0 f 0 - ... repeat pattern nrc + 1,...4 until *2 nrc - 1, truncate if necessary 1 2*nrc repeat sub-loop 0, use ba[2:0] = 1 instead 2 4*nrc repeat sub-loop 0, use ba[2:0] = 2 instead 3 6*nrc repeat sub-loop 0, use ba[2:0] = 3 instead 4 8*nrc repeat sub-loop 0, use ba[2:0] = 4 instead 5 10*nrc repeat sub-loop 0, use ba[2:0] = 5 instead 6 12*nrc repeat sub-loop 0, use ba[2:0] = 6 instead 7 14*nrc repeat sub-loop 0, use ba[2:0] = 7 instead
rev. 0.1 / apr 2013 22 table 5 - idd2n and idd3n measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are mid-level. b) dq signals are mid-level. table 6 - idd2nt and iddq2n t measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are mid-level. b) dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 d10000000000 - 1d10000000000- 2d 111 1 0 0 0 0 0 f 0 - 3d 111 1 0 0 0 0 0 f 0 - 1 4-7 repeat sub-loop 0, use ba[2:0] = 1 instead 2 8-11 repeat sub-loop 0, use ba[2:0] = 2 instead 3 12-15 repeat sub-loop 0, use ba[2:0] = 3 instead 4 16-19 repeat sub-loop 0, use ba[2:0] = 4 instead 5 20-23 repeat sub-loop 0, use ba[2:0] = 5 instead 6 24-17 repeat sub-loop 0, use ba[2:0] = 6 instead 7 28-31 repeat sub-loop 0, use ba[2:0] = 7 instead ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 d10000000000 - 1d10000000000- 2d 1111 0 0 0 0 0 f 0 - 3d 1111 0 0 0 0 0 f 0 - 1 4-7 repeat sub-loop 0, but odt = 0 and ba[2:0] = 1 2 8-11 repeat sub-loop 0, bu t odt = 1 and ba[2:0] = 2 3 12-15 repeat sub-loop 0, but odt = 1 and ba[2:0] = 3 4 16-19 repeat sub-loop 0, but odt = 0 and ba[2:0] = 4 5 20-23 repeat sub-loop 0, but odt = 0 and ba[2:0] = 5 6 24-17 repeat sub-loop 0, but odt = 1 and ba[2:0] = 6 7 28-31 repeat sub-loop 0, but odt = 1 and ba[2:0] = 7
rev. 0.1 / apr 2013 23 table 7 - idd4r and iddq4r measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are used according to rd commands, otherwise mid-level. b) burst sequence driven on each dq signal by read co mmand. outside burst operation, dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 rd 0 1 0 1 0 0 00 0 0 0 0 00000000 1d100000000000- 2,3 d ,d 1111 0 0000 0 0 0 - 4 rd 0 1 0 1 0 0 00 0 0 f 0 00110011 5d1000000000f0- 6,7 d ,d 1111 0 0000 0 f 0 - 1 8-15 repeat sub-loop 0, but ba[2:0] = 1 2 16-23 repeat sub-loop 0, but ba[2:0] = 2 3 24-31 repeat sub-loop 0, but ba[2:0] = 3 4 32-39 repeat sub-loop 0, but ba[2:0] = 4 5 40-47 repeat sub-loop 0, but ba[2:0] = 5 6 48-55 repeat sub-loop 0, but ba[2:0] = 6 7 56-63 repeat sub-loop 0, but ba[2:0] = 7
rev. 0.1 / apr 2013 24 table 8 - idd4w measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are used according to wr commands, otherwise mid-level. b) burst sequence driven on each dq signal by write co mmand. outside burst operation, dq signals are mid-level. table 9 - idd5b measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are mid-level. b) dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 wr 0 1 0 0 1 0 00 0 0 0 0 00000000 1d100010000000- 2,3 d ,d 1111 1 0000 0 0 0 - 4 wr 0 1 0 0 1 0 00 0 0 f 0 00110011 5d1000100000f0- 6,7 d ,d 1111 1 0000 0 f 0 - 1 8-15 repeat sub-loop 0, but ba[2:0] = 1 2 16-23 repeat sub-loop 0, but ba[2:0] = 2 3 24-31 repeat sub-loop 0, but ba[2:0] = 3 4 32-39 repeat sub-loop 0, but ba[2:0] = 4 5 40-47 repeat sub-loop 0, but ba[2:0] = 5 6 48-55 repeat sub-loop 0, but ba[2:0] = 6 7 56-63 repeat sub-loop 0, but ba[2:0] = 7 ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 ref 0 0 0 1 0 0 0 0 0 0 0 - 11.2 d, d 1 0 0 0 0 0 00 0 0 0 0 - 3,4 d , d 1111 0 0000 0 f 0 - 5...8 repeat cycles 1...4, but ba[2:0] = 1 9...12 repeat cycles 1...4, but ba[2:0] = 2 13...16 repeat cycles 1...4, but ba[2:0] = 3 17...20 repeat cycles 1...4, but ba[2:0] = 4 21...24 repeat cycles 1...4, but ba[2:0] = 5 25...28 repeat cycles 1...4, but ba[2:0] = 6 29...32 repeat cycles 1...4, but ba[2:0] = 7 2 33...nrfc-1 repeat sub-loop 1, until nrfc - 1. truncate, if necessary.
rev. 0.1 / apr 2013 25 table 10 - idd7 meas urement-loop pattern a) attention! sub-loops 10-19 have inverse a[6:3] pattern and data pattern than sub-loops 0-9 a) dm must be driven low all the time. dqs, dqs are used according to rd commands, otherwise mid-level. b) burst sequence driven on each dq signal by read co mmand. outside burst operation, dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 act 0 0 1 1 0 0 00 0 0 0 0 - 1 rda 0 1 0 1 0 0 00 1 0 0 0 00000000 2 d 1 0 0 0 0 0 00 0 0 0 0 - ... repeat above d command until nrrd - 1 1 nrrd act 0 0 1 1 0 1 00 0 0 f 0 - nrrd+1 rda 0 1 0 1 0 1 00 1 0 f 0 00110011 nrrd+2 d 1 0 0 0 0 1 00 0 0 f 0 - ... repeat above d command until 2* nrrd - 1 2 2*nrrd repeat sub-loop 0, but ba[2:0] = 2 3 3*nrrd repeat sub-loop 1, but ba[2:0] = 3 4 4*nrrd d 1 0 0 0 0 3 00 0 0 f 0 - assert and repeat above d command until nfaw - 1, if necessary 5 nfaw repeat sub-loop 0, but ba[2:0] = 4 6 nfaw+nrrd repeat sub-loop 1, but ba[2:0] = 5 7 nfaw+2*nrrd repeat sub-loop 0, but ba[2:0] = 6 8 nfaw+3*nrrd repeat sub-loop 1, but ba[2:0] = 7 9 nfaw+4*nrrd d 1 0 0 0 0 7 00 0 0 f 0 - assert and repeat above d command until 2* nfaw - 1, if necessary 10 2*nfaw+0 act 0 0 1 1 0 0 00 0 0 f 0 - 2*nfaw+1 rda 0 1 0 1 0 0 00 1 0 f 0 00110011 2&nfaw+2 d 1 0 0 0 0 0 00 0 0 f 0 - repeat above d command until 2* nfaw + nrrd - 1 11 2*nfaw+nrrd act 0 0 1 1 0 1 00 0 0 0 0 - 2*nfaw+nrrd+1 rda 0 1 0 1 0 1 00 1 0 0 0 00000000 2&nfaw+nrrd+ 2 d 1 0 0 0 0 1 00 0 0 0 0 - repeat above d command until 2* nfaw + 2* nrrd - 1 12 2*nfaw+2*nrrd repeat sub-loop 10, but ba[2:0] = 2 13 2*nfaw+3*nrrd repeat sub-loop 11, but ba[2:0] = 3 14 2*nfaw+4*nrrd d 1 0 0 0 0 3 00 0 0 0 0 - assert and repeat above d command until 3* nfaw - 1, if necessary 15 3*nfaw repeat sub-loop 10, but ba[2:0] = 4 16 3*nfaw+nrrd repeat sub-loop 11, but ba[2:0] = 5 17 3*nfaw+2*nrrd repeat sub-loop 10, but ba[2:0] = 6 18 3*nfaw+3*nrrd repeat sub-loop 11, but ba[2:0] = 7 19 3*nfaw+4*nrrd d 1 0 0 0 0 7 00 0 0 0 0 - assert and repeat above d command until 4* nfaw - 1, if necessary
rev. 0.1 / apr 2013 26 idd specifications idd values are for full operating range of voltage and temperature unless otherwise noted. i dd specification notes: 1. applicable for mr2 settings a6=0 and a7=0. temperature range for idd6 is 0 - 85 o c. 2. applicable for mr2 settings a6=0 and a7=1. temperature range for idd6et is 0 - 95 o c. speed grade bin ddr3 - 1066 7-7-7 ddr3 - 1333 9-9-9 ddr3 - 1600 11-11-11 ddr3 - 1600 11-11-11 unit notes symbol max. max. max. max. i dd0 55 57 59 61 ma x4/8 74 76 79 80 ma x16 i dd01 63 64 67 70 ma x4/8 86 88 90 92 ma x16 i dd2p0 22 22 22 22 ma x4/8 34 34 34 34 ma x16 i dd2p1 24 26 26 28 ma x4/8 36 36 38 40 ma x16 i dd2n 40 40 42 44 ma x4/8 52 54 58 58 ma x16 i dd2nt 44 48 52 54 ma x4/8 60 62 68 72 ma x16 i dd2q 40 42 44 42 ma x4/8 54 54 58 60 ma x16 i dd3p 40 40 42 42 ma x4/8 46 46 48 50 ma x16 i dd3n 56 58 62 64 ma x4/8 64 66 70 74 ma x16 i dd4r 90 105 116 132 ma x4/8 131 152 174 194 ma x16 i dd4w 95 110 121 137 ma x4/8 141 162 184 204 ma x16 i dd5b 220 220 221 222 ma x4/8 226 227 229 229 ma x16 i dd6 30 30 30 30 ma x4/8, 1 38 38 388 38 ma x16, 1 i dd6et 38 38 38 38 ma x4/8, 2 46 46 46 46 ma x16, 2 i dd7 140 165 171 182 ma x4/8 211 242 249 254 ma x16
rev. 0.1 / apr 2013 27 input/output capacitance parameter symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 ddr3-1866 units notes min max min max min max min max min max input/output capacitance (dq, dm, dqs, dqs , tdqs, tdqs ) c io 1.4 3.0 1.4 2.7 1.4 2.5 1.4 2.3 1.4 2.2 pf 1,2,3 input capacitance, ck and ck c ck 0.8 1.6 0.8 1.6 0.8 1.4 0.8 1.4 0.8 1.3 pf 2,3 input capacitance delta ck and ck c dck 0 0.15 0 0.15 0 0.15 0 0.15 0 0.15 pf 2,3,4 input capacitance delta, dqs and dqs c ddqs 00.2000.2000.1500.1500.15 pf 2,3,5 input capacitance (all other input-only pins) c i 0.75 1.4 0.75 1.35 0.75 1.3 0.75 1.3 0.75 1.2 pf 2,3,6 input capacitance delta (all ctrl input-only pins) c di_ctr l -0.5 0.3 -0.5 0.3 -0.4 0.2 -0.4 0.2 -0.4 0.2 pf 2,3,7,8 input capacitance delta (all add/cmd input-only pins) c di_add _cmd -0.5 0.5 -0.5 0.5 -0.4 0.4 -0.4 0.4 -0.4 0.4 pf 2,3,9,10 input/output capacitance delta (dq, dm, dqs, dqs ) c dio -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 pf 2,3,11 input/output capacitance of zq pin c zq - 3 - 3 - 3 - 3 - 3 pf 2,3,12 notes: 1. although the dm, tdqs and tdqs pins have different functions, the loading matches dq and dqs. 2. this parameter is not subject to prod uction test. it is verified by design and characterization. the capacitance is ? measured according to jep147(?procedure for measuring input capacitance using a vector network ? analyzer(vna)?) with vdd, vddq, vss,vssq applied an d all other pins floating (except the pin under test, cke, ? reset and odt as necessary). vdd=vddq=1.5v, vbias=vdd/2 and on-die termination off. 3. this parameter applies to mono lithic devices only; st acked/dual-die devices are not covered here 4. absolute value of c ck -c ck . 5. absolute value of c io (dqs)-c io (dqs ). 6. c i applies to odt, cs , cke, a0-a15, ba0-ba2, ras , cas , we . 7. c di_ctr applies to odt, cs and cke. 8. c di_ctrl =c i (cntl) - 0.5 * c i (clk) + c i (clk )) 9. c di_add_cmd applies to a0-a15, ba0-ba2, ras , cas and we . 10. c di_add_cmd =c i (add_cmd) - 0.5*(c i (clk)+c i (clk )) 11. c dio =c io (dq) - 0.5*(c io (dqs)+c io (dqs )) 12. maximum external load capacitance an zq pin: 5 pf.
rev. 0.1 / apr 2013 28 standard speed bins ddr3l sdram standard speed bins include tck, trcd , trp, tras and trc for each corresponding bin. ddr3-800 speed bins for specific notes see "speed bin table notes" on page 33. speed bin ddr3-800e unit notes cl - nrcd - nrp 6-6-6 parameter symbol min max internal read command to first data t aa 15 20 ns act to internal read or write delay time t rcd 15 ? ns pre command period t rp 15 ? ns act to act or ref command period t rc 52.5 ? ns act to pre command period t ras 37.5 9 * trefi ns cl = 5 cwl = 5 t ck(avg) 3.0 3.3 ns 1,2,3,4,11,12 cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1,2,3 supported cl settings 5, 6 n ck 12 supported cwl settings 5 n ck
rev. 0.1 / apr 2013 29 ddr3-1066 speed bins for specific notes see "speed bin table notes" on page 33. speed bin ddr3-1066f unit note cl - nrcd - nrp 7-7-7 parameter symbol min max internal read command to first data t aa 13.125 20 ns act to internal read or write delay time t rcd 13.125 ? ns pre command period t rp 13.125 ? ns act to act or ref command period t rc 50.625 ? ns act to pre command period t ras 37.5 9 * trefi ns cl = 5 cwl = 5 t ck(avg) 3.0 3.3 ns 1,2,3,4,6,11,12 cwl = 6 t ck(avg) reserved ns 4 cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1,2,3,6 cwl = 6 t ck(avg) reserved ns 1,2,3,4 cl = 7 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1,2,3,4 cl = 8 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1,2,3 supported cl settings 5, 6, 7, 8 n ck 12 supported cwl settings 5, 6 n ck
rev. 0.1 / apr 2013 30 ddr3-1333 speed bins for specific notes see "speed bin table notes" on page 33. speed bin ddr3-1333h unit note cl - nrcd - nrp 9-9-9 parameter symbol min max internal read command to first data t aa 13.5 (13.125) 5,10 20 ns act to internal read or write delay time t rcd 13.5 (13.125) 5,10 ?ns pre command period t rp 13.5 (13.125) 5,10 ?ns act to act or ref command period t rc 49.5 (49.125) 5,10 ?ns act to pre command period t ras 36 9 * trefi ns cl = 5 cwl = 5 t ck(avg) 3.0 3.3 ns 1,2,3,4,7,11,12 cwl = 6, 7 t ck(avg) reserved ns 4 cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1,2,3,7 cwl = 6 t ck(avg) reserved ns 1,2,3,4,7 cwl = 7 t ck(avg) reserved ns 4 cl = 7 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1,2,3,4,7 (optional) 5,10 cwl = 7 t ck(avg) reserved ns 1,2,3,4 cl = 8 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1,2,3,7 cwl = 7 t ck(avg) reserved ns 1,2,3,4 cl = 9 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1,2,3,4 cl = 10 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1,2,3 (optional) ns 5 supported cl settings 5, 6, 7, 8, 9, 10 n ck supported cwl settings 5, 6, 7 n ck
rev. 0.1 / apr 2013 31 ddr3-1600 speed bins for specific notes see "speed bin table notes" on page 33. speed bin ddr3-1600k unit note cl - nrcd - nrp 11-11-11 parameter symbol min max internal read command to first data t aa 13.75 (13.125) 5,10 20 ns act to internal read or write delay time t rcd 13.75 (13.125) 5,10 ?ns pre command period t rp 13.75 (13.125) 5,10 ?ns act to act or ref command period t rc 48.75 (48.125) 5,10 ?ns act to pre command period t ras 35 9 * trefi ns cl = 5 cwl = 5 t ck(avg) 3.0 3.3 ns 1,2,3,4,8,11,12 cwl = 6, 7 t ck(avg) reserved ns 4 cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1,2,3,8 cwl = 6 t ck(avg) reserved ns 1,2,3,4,8 cwl = 7 t ck(avg) reserved ns 4 cl = 7 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1,2,3,4,8 (optional) 5,10 cwl = 7 t ck(avg) reserved ns 1,2,3,4,8 cwl = 8 t ck(avg) reserved ns 4 cl = 8 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1,2,3,8 cwl = 7 t ck(avg) reserved ns 1,2,3,4,8 cwl = 8 t ck(avg) reserved ns 1,2,3,4 cl = 9 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1,2,3,4,8 (optional) 5,10 cwl = 8 t ck(avg) reserved ns 1,2,3,4 cl = 10 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1,2,3,8 cwl = 8 t ck(avg) reserved ns 1,2,3,4 cl = 11 cwl = 5, 6,7 t ck(avg) reserved ns 4 cwl = 8 t ck(avg) 1.25 <1.5 ns 1,2,3 supported cl settings 5, 6, 7, 8, 9, 10, 11 n ck supported cwl settings 5, 6, 7, 8 n ck
rev. 0.1 / apr 2013 32 ddr3-1866 speed bins for specific notes see "speed bin table notes" on page 33. speed bin ddr3-1866m unit note cl - nrcd - nrp 13-13-13 parameter symbol min max internal read command to first data t aa 13.91 (13.125) 5,13 20 ns act to internal read or write delay time t rcd 13.91 (13.125) 5,13 ?ns pre command period t rp 13.91 (13.125) 5,13 ?ns act to pre command period t ras 34 9 * trefi ns act to act or pre command period t rc 47.91 (47.125) 5,13 -ns cl = 5 cwl = 5 t ck(avg) 3.0 3.3 ns 1, 2, 3, 4, 9 cwl = 6,7,8,9 t ck(avg) reserved ns 4 cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1, 2, 3, 9 cwl = 6 t ck(avg) reserved ns 1, 2, 3, 4, 9 cwl = 7,8,9 t ck(avg) reserved ns 4 cl = 7 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1, 2, 3, 4, 9 (optional) cwl = 7,8,9 t ck(avg) reserved ns 4 cl = 8 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1, 2, 3, 9 cwl = 7 t ck(avg) reserved ns 1, 2, 3, 4, 9 cwl = 8,9 t ck(avg) reserved ns 4 cl = 9 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1, 2, 3, 4, 9 (optional) cwl = 8 t ck(avg) reserved ns 1, 2, 3, 4, 9 cwl = 9 t ck(avg) reserved ns 4 cl = 10 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1, 2, 3, 9 cwl = 8 t ck(avg) reserved ns 1, 2, 3, 4, 9 cl = 11 cwl = 5,6,7 t ck(avg) reserved ns 4 cwl = 8 t ck(avg) 1.25 <1.5 ns 1, 2, 3, 4, 9 (optional) cwl = 9 t ck(avg) reserved ns 1, 2, 3, 4 cl = 12 cwl = 5,6,7,8 t ck(avg) reserved ns 4 cwl = 9 t ck(avg) reserved ns 1,2,3,4 cl = 13 cwl = 5,6,7,8 t ck(avg) reserved ns 4 cwl = 9 t ck(avg) 1.07 <1.25 ns 1, 2, 3 supported cl settings 6, 7, 8, 9, 10, 11, 13 n ck supported cwl settings 5, 6, 7, 8, 9 n ck
rev. 0.1 / apr 2013 33 speed bin table notes ? absolute specification (t oper ; v ddq = v dd = 1.5v +/- 0.075 v); 1. the cl setting and cwl setting result in tck(avg).min and tck(avg).max requirements. when mak - ing a selection of tck(avg), both need to be fulfille d: requirements from cl setting as well as require - ments from cwl setting. 2. tck(avg).min limits: since cas latency is not pure ly analog - data and strobe output are synchro - nized by the dll - all possible intermediate freque ncies may not be guaranteed. an application should use the next smaller jedec standard tck(avg) valu e (3.0, 2.5, 1.875, 1.5, or 1.25 ns) when calculat - ing cl [nck] = taa [ns] / tck(avg) [ns], rounding up to the next ?supported cl?, where tck(avg) = 3.0 ns should only be used for cl = 5 calculation. 3. tck(avg).max limits: calculate tck(avg) = taa.ma x / cl selected and round the resulting tck(avg) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). this result is tck(avg).max corresponding to cl selected. 4. ?reserved? settings are not allowed. user must program a different value. 5. ?optional? settings allow certain devices in the indust ry to support this setting, however, it is not a man - datory feature. refer to dimm data sheet and/or th e dimm spd information if and how this setting is supported. 6. any ddr3-1066 speed bin also supports functional op eration at lower frequencies as shown in the table which are not subject to production te sts but verified by de sign/characterization. 7. any ddr3-1333 speed bin also supports functional op eration at lower frequencies as shown in the table which are not subject to production te sts but verified by de sign/characterization. 8. any ddr3-1600 speed bin also supports functional op eration at lower frequencies as shown in the table which are not subject to production test s but verified by desi gn/characterization. 9. any ddr3-1866 speed bin also supports functional op eration at lower frequencies as shown in the table which are not subject to production te sts but verified by de sign/characterization. 10. ddr3 sdram devices supporting optional down binni ng to cl=7 and cl=9, and taa/trcd/trp must be 13.125 ns or lower. spd settings must be programmed to match. for example, ddr3-1333h devices supporting down binning to ddr3-1066f shou ld program 13.125 ns in spd bytes for taamin (byte 16), trcdmin (byte 18), and trpmin (byte 20) . ddr3-1600k devices supporting down binning to ddr3-1333h or ddr3-1600f should program 13.125 ns in spd bytes for taamin (byte 16), trcdmin (byte 18), and trpmin (byte 20). once trp (byte 20) is programmed to 13.125ns, trcmin (byte 21,23) also should be programmed accordingly. for ex ample, 49.125ns (trasmin + trpmin = 36 ns + 13.125 ns) for ddr3-1333h and 48.125ns (trasmin + trpmin = 35 ns + 13.125 ns) for ddr3-1600k. 11. ddr3 800 ac timing apply if dram operat es at lower than 800 mt/s data rate. 12. for cl5 support, refer to dimm spd information. dram is required to support cl5. cl5 is not manda - tory in spd coding. 13. ddr3 sdram devices supporting opti onal down binning to cl=11, cl=9 and cl=7, taa/trcd/trpmin must be 13.125ns. spd setting must be programed to match. for example, ddr3-1866m devices sup - porting down binning to ddr3-1600k or ddr3- 1333h or 1066f should program 13.125ns in spd bytes for taamin(byte 16), trcdmin(byte 18) and trpmin(byte 20) is programmed to 13.125ns, trc - min(byte 21,23) also should be programmed accord ingly. for example, 47.125ns (trasmin + trpmin = 34ns + 13.125ns)
rev. 0.1 / apr 2013 34 package dimensions package dimension(x4/x8): 78ball fi ne pitch ball grid array outline a1 index mark 9.000 0.100 ? 11.100 0.100 ? 0.290 0.050 ? 1.100 0.100 ? 987 21 a b c d e f g h j k l m n 0.800 x 8 = 6.400 0.800 1.600 0.800 x 12 = 9.600 0.800 1.600 78 x ? 0.400 0.050 ? 0.750 0.100 ? top view bottom view side view a1 ball mark 3 1.300 0.100 ?
rev. 0.1 / apr 2013 35 package dimension(x16): 96ball fi ne pitch ball grid array outline 9.000 0.100 ? 13.000 0.100 ? 987 21 a b c d e f g h j k l m n 1.300 0.100 ? 0.800 x 8 = 6.400 0.800 1.600 0.800 x 15 = 12.000 0.800 1.600 96 x ? 0.400 0.050 ? 0.500 0.100 ? top view bottom view side view a1 ball mark 3 o p q a1 index mark 0.290 0.050 ? 1.100 0.100 ?

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